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74LCX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS
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5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 5.4 ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V
TSSOP
ORDER CODES
PACKAGE TSSOP TUBE T &R 74LCX16373TTR
PIN CONNECTION
DESCRIPTION The 74LCX16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken LOW, the nQ outputs will be latched precisely at the logic level of D input data. While the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
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74LCX16373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1 SYMBOL 1OE NAME AND FUNCTION
IEC LOGIC SYMBOLS
2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage
3 State Output Enable Input (Active LOW) 1Q0 to 1Q7 3-State Outputs
TRUTH TABLE
INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE * L H
X : Don`t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level.
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74LCX16373
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol V CC VI VO VO IIK IOK IO ICC IGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (OFF State) DC Output Voltage (High or Low State) (note 1) DC Input Diode Current DC Output Diode Current (note 2) DC Output Current DC Supply Current per Supply Pin DC Ground Current per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 50 - 50 50 100 100 -65 to +150 300 Unit V V V V mA mA mA mA mA C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND
RECOMMENDED OPERATING CONDITIONS
Symbol V CC VI VO VO IOH, IOL IOH, IOL Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage (OFF State) Output Voltage (High or Low State) High or Low Level Output Current (V CC = 3.0 to 3.6V) High or Low Level Output Current (V CC = 2.7V) Operating Temperature Input Rise and Fall Time (note 2) Parameter Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -55 to 125 0 to 10 Unit V V V V mA mA C ns/V
1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V
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74LCX16373
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) -40 to 85 C Min. 2.0 2.7 to 3.6 0.8 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 II Ioff IOZ Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input 2.7 to 3.6 0 2.7 to 3.6 I O=-100 A IO=-12 mA IO=-18 mA IO=-24 mA IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5V V I or VO = 5.5V V I = VIH or VIL VO = 0 to VCC VI = VCC or GND VI or VO= 3.6 to 5.5V VIH = VCC - 0.6V VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 5 20 20 500 VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 5 20 20 500 A A A A A V V 0.8 V Max. Value -55 to 125 C Min. 2.0 Max. V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
ICC ICC
2.7 to 3.6 2.7 to 3.6
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 CL = 50pF VIL = 0V, V IH = 3.3V Value TA = 25 C Min. Typ. 0.8 -0.8 Max. V Unit
VOLP V OLV
Dynamic Low Level Quiet Output (note 1)
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.
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74LCX16373
AC ELECTRICAL CHARACTERISTICS
Test Conditi on Symbol Parameter VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 50 50 50 500 500 500 2.5 2.5 2.5 50 500 2.5 50 500 2.5 CL (pF) 50 50 50 RL () 500 500 500 ts = t r (ns) 2.5 2.5 2.5 -40 to 85 C Min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 3.0 3.0 1.0 Max. 5.9 5.4 6.4 5.5 6.5 6.1 6.3 6.0 Value -55 to 125 C Min. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 1.5 1.5 3.0 3.0 1.0 ns ns ns ns Max. 5.9 5.4 6.4 5.5 6.5 6.1 6.3 6.0 ns ns ns ns Unit
tPLH tPHL tPLH tPHL tPZL tPZH
Propagation Delay Time (Dn to Qn) Propagation Delay Time (LE to Qn) Output Enable Time to HIGH and LOW level Output Disable Time from HIGH to LOW level Set-Up Time, HIGH or LOW level (Dn to LE) Hold Time, HIGH or LOW level (Dn to LE) LE Pulse Width, HIGH Output To Output Skew Time (note1, 2)
tPLZ tPHZ
tS
th
tW tOSLH tOSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 VIN = 0 to VCC VIN = 0 to VCC fIN = 10MHz V IN = 0 or VCC Value TA = 25 C Min. Typ. 7 8 20 Max. pF pF pF Unit
CIN C OUT CPD
Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit)
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74LCX16373
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
C L = 50 pF or equivalent (includes jig and probe capacitance) R L = R1 = 500 or equivalent R T = ZOUT of pulse generator (typically 50)
SWITCH Open 6V GND
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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74LCX16373
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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74LCX16373
TSSOP48 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 0.17 0.09 12.4 7.95 6.0 0.5 BSC 8 0.75 0 0.020 0.05 0.9 0.27 0.20 12.6 8.25 6.2 0.0067 0.0035 0.408 0.313 0.236 0.0197 BSC 8 0.030 TYP MAX. 1.1 0.15 0.002 0.035 0.011 0.0079 0.496 0.325 0.244 MIN. TYP. MAX. 0.043 0.006 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1 7065588A
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74LCX16373
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom (c) http://w ww.st.com
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